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| Bookly Micro 32 Megabit (4M x 8/2M x 16) Flash Memory AC29LV320B/T 3.0 Volt-Only Boot Sector Flash Memory DEVICE FEATURES Organized as 2M x 16 / 4M x 8 Single Voltage Read and Write Operations 2.7~3.6V power supply Sector Architecture Byte Mode (4M x 8): Eight 8 Kbyte and sixty-three 64 Kbyte sectors Word Mode (2M x 16): Eight 4 Kword and sixty-three 32 Kword sectors Page Mode: 2 Kword (or 4 Kbyte) per-page, total 1,024 pages Top or Bottom Boot Block Configuration Read Access Time Access time: 90ns and 120ns Power Consumption Automatic sleep mode current: 200 nA Standby mode current: 200 nA Active read current (at 1 MHz): 2 mA Active read current (at 5 MHz): 10 mA Erase Features Any combinations of sectors can be erased Unlock Bypass Program Command Reduce overall programming time when issuing multiple program command sequences End-of-Program or End-of-Erase Software Detection Data# Polling Toggle Bit End-of-Program or End-of-Erase Hardware Detection Ready/Busy# Pin (RY/BY#) Hardware Reset (Reset#) Hardware method to reset the device to reading array data WP#/ACC Input Pin Write protect (WP#) function allows protection of two outermost boot sectors, regardless of sector protect status Acceleration (ACC) function accelerates program time Sector Protection Using hardware method to lock a sector and prevent any program or erase operation within that sector. Sectors can be locked in system or via programming equipment. Temporary Sector Unprotect feature allows code changes in previously locked sectors. JEDEC Standard Pin-out and software compatible with single-power-supply flash memory High reliability Endurance cycles: 100K (typical) Data retention at 125C: 10-year Package Options 48-Pin TSOP 48-Ball FBGA - - - - - - - This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 1 AC29LV320B/T PRODUCT DESCRIPTION The AC29LV320 is a 32-Megabit, 3.0 volt-only flash memory, organized as 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits each. The word mode data (x16) appears on DQ15-DQ0, and the byte mode data (x8) appears on DQ7-DQ0. The device can be programmed in-system using 3.0-volt single VCC supply. No VPP is required for write or erase operation. The device can also be programmed in standard EPROM programmers. The device offers access times of 90 or 120 ns. The device has separate control signals, chip enable (CE#), write enable (WE#) and output enable (OE#), to eliminate bus contention. The device requires a 3.0-volt single power supply for both read and write operations. Both the program and erase operations are performed using the internally generated high voltages. The device has command set that is compatible with the JEDEC single-power-supply Flash standard. The write cycles latch addresses and data needed for programming and erase operations. To read data from the device is similar to reading from other Flash or EPROM devices. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (Toggle Bits) status bits. After a program or erase cycle has been completed, the device is ready to read array data or to accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The page erase feature allows memory pages to be erased and reprogrammed without affecting the data contents of other pages. Hardware data protection feature includes a low VCC detector that automatically inhibits write operation during power transition. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved during in-system operation or via programming equipment. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Both modes reduce greatly the power consumption. The device is offered in package types of 48-ball FBGA and 48-pin TSOP. PRODUCT SELECTOR GUIDE Part Number Speed Option (Standard Voltage Range: VCC=2.7~3.6V) Max Access Time (ns) CE# Access (ns) OE# Access (ns) AC29LV320 90 90 90 40 120 120 120 50 This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 2 AC29LV320B/T ORDERING INFORMATION Standard Products The order number is defined by a combination of the following elements. AC29LV320 T -- 90 E C Optional Processing Blank= Standard Processing B = Burn-in N = 16-byte ESN devices Temperature Range C = Commercial (0C to 70C) I = Industrial (-40C to +85C) E = Extended (-55C to +125C) Package Type E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS048) WM = 48-Ball Fine Pitch Ball Grid Array (FBGA) 0.80 mm pitch, 6 x 12 mm package (FBD048) Speed Option See Product Selector Guide and Valid Combinations Boot Code Sector Architecture T = Top Sector B = Bottom Sector Device Number/Description AC29LV320 32 Megabit (4M x 8/2M x 16) Flash Memory 3.0 Volt-only Read, Program and Erase Valid Combinations for TSOP Packages AC29LV320T-90 AC29LV320B-90 AC29LV320T-120 AC29LV320B-120 EC, EI EC, EI, EE Valid Combinations for FBGA Packages Order Number AC29LV320T-90 WMC, AC29LV320B-90 WMI WMC, AC29LV320T-120 WMI, AC29LV320B-120 WME Package Marking CL320T-90 C, I CL320B-90 CL320T-12 CL320B-12 C, I, E Valid Combinations: The Valid Combinations list the configurations to be supported in volume. Consult Actrans System Inc. sales office to confirm availability of any specific valid combination or to check newly released combination. This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 3 AC29LV320B/T Functional Block Diagram RY/BY# V CC V SS Reset# Sector Switches DQ0-DQ15(A -1) Erase Voltage Generstor Input/Output Buffers State Control W E# B YTE# Com m and register PGM Voltage Generator Chip Enable Output Enable Logic Data Latch STB CE# O E# STB Address Latch V CC Detector Tim er Y-Decoder Y-G ating A0-A20 X-Decoder Cell M atrix This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 4 AC29LV320B/T Connection Diagrams A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RESET# NC WP#/ACC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 Standard TSOP A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Reserve TSOP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RESET# NC WP#/ACC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 5 AC29LV320B/T Connection Diagrams 48-Ball FBGA Top View, Balls Facing Down A6 B6 C6 D6 E6 F6 G6 H6 A13 A5 A12 B5 A14 C5 A15 D5 A16 BYTE# DQ15/A-1 VSS E5 F5 G5 H5 A9 A4 A8 B4 A10 C4 A11 D4 DQ7 E4 DQ14 F4 DQ13 G4 DQ6 H4 WE# A3 RESET# NC B3 C3 A19 D3 DQ5 E3 DQ12 F3 VCC G3 DQ4 H3 RY/BY# WP#/ACC A18 A2 B2 C2 A20 D2 DQ2 E2 DQ10 F2 DQ11 G2 DQ3 H2 A7 A1 A17 B1 A6 C1 A5 D1 DQ0 E1 DQ8 F1 DQ9 G1 DQ1 H1 A3 A4 A2 A1 A0 CE# OE# VSS This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 6 AC29LV320B/T Special Handling Instructions for Fine Pitch Ball Grid Array (FBGA) Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged period of time. PIN DESCRIPTION A0-A20 DQ0-DQ14 DQ15/A-1 BYTE# CE# OE# WE# RESET# RY/BY# VCC VSS NC WP#/ACC = 21 addresses = 15 data inputs/outputs = DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) = Select 8-bit or 16-bit mode = Chip enable = Output enable = Write enable = Hardware reset pin, active low = Ready/Busy# output = 3.0-volt single power supply = Device ground = Pin not connected internally = Write protect/ Acceleration program Logic Symbol 21 A0-A20 DQ0DQ15 (A-1) 16 or 8 CE# OE# W E# RESET# BYTE# W P#/ACC RY/BY# This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 7 AC29LV320B/T DEVICE OPERATION The device operations are initiated through internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, and the address and data information that is needed to execute the command. The contents of the register serve as inputs to the internal state machine. The outputs of state machine dictate the function of the device. Table 1 lists the device operations, the inputs and control levels they require, and the resulting output. bits are don't care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasing begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data. Word/Byte Configuration The BYTE# pin controls the device data I/O pins DQ15-DQ0 to operate either in byte or word configuration. If the BYTE# pin is set at logic `1', the device is in word configuration, and DQ15- DQ0 are active and controlled by CE# and OE#. If the BYTE# pin is set at logic `0', the device is in byte configuration, and only data I/O pins DQ0- DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8-DQ14 are in tri-state, and the DQ15 pin is used as an input for the LSB (A-1) address function. Write Command/Command Sequence Writing specific address and data commands or sequences into the command register initiates device operations. Table 11 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must set WE# and CE# to VIL, and OE# to VIH. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the "AC Characteristics" section. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contains timing specification tables and timing diagrams for the write operations. Read To read array data from the outputs, the system must set the CE# and OE# pins to VIL. CE# is the power control, which selects the device. OE# is the output control, which gates array data to the output pins. The WE# should remain at VIH. The BYTE# pin determines whether the device outputs array data in words or bytes. The internal state machine is set to read array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is required in this mode to obtain array data. The device remains enabled for read access until the command register contents are altered. The device is also ready to read array data after completing a Program or Erase operation. The Read Operations table provides the read parameters, and Figure 11 shows the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data. Word/Byte Program The system may program the device by word or byte, depending on the state of the BYTE# pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next. Table 11 shows the address and data requirements for the byte program command sequence. When the Program operation is complete, Reset Writing the reset command to the device resets the device to the read mode. The address This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 8 AC29LV320B/T the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6 or RY/BY#. See "Write Operation Status" for information on these status bits. Note that a hardware reset immediately terminates the programming operation. In order to ensure data integrity, the Byte Program command sequence should be reinitiated once the device has reset to reading array data. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a "0" back to a "1". Attempting to do so may cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still "0". Only erase operations can convert a "0" to a "1". START Write Program Command Sequence Increment Address No Last Address? Yes Unlock Bypass The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles, followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 11 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the program address and the data 90h. The second cycle need only contain the data 00h. The device then returns to reading array data. Figure 1 illustrates the algorithm for the program operation. See the Erase/Program Programming Completed Figure 1. Program Operation Note: See Table 11 for program command sequence. Operations table in "AC Characteristics" for parameters, and to Figure 15 for timing diagrams. Accelerated Program Operation The device offers accelerated program operation through the ACC function, which is one of the two functions provided by the WP#/ACC pin. This ACC function allows a faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, which temporarily unprotects any protected sectors and uses the high voltage VHH on the pin to reduce the time required for program operation. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to the normal operation. Note that the WP#/ACC pin must not be set at VHH for operations other than the accelerated program; otherwise the device may be damaged. This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 9 AC29LV320B/T Table 1. AC29LV320 Device Operations Operation Read Write Accelerated Program Standby Output Disable Reset Sector Protect (Note 2) Sector Unprotect (Note 2) Temporary Sector Unprotect CE# OE# WE# Reset# WP#/ACC L L L VCC 0.3V L X L L X L H H X H X H H X H L L X H X L L X H H H VCC 0.3V H L VID VID VID L/H (Note 3) VHH H L/H L/H L/H (Note 3) (Note 3) Addresses (Note 2) AIN AIN AIN X X X SA, A6=L, A1=H, A0=L SA, A6=H, A1=H, A0=L AIN DQ8-DQ15 Byte# Byte# =VIH =VIL DOUT DOUT DQ8-DQ14 (Note 4) (Note 4) =High-Z, (Note 4) (Note 4) DQ15=A-1 DQ0 ~ DQ7 High-Z High-Z High-Z (Note 4) (Note 4) High-Z High-Z High-Z X X High-Z High-Z High-Z X X High-Z (Note 4) (Note 4) Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5~12.5 V, VHH = 11.5~12.5 V, X = Don't Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Addresses are A20:A0 in word mode (BYTE# = VIH), A20:A-1 in byte mode (BYTE# = VIL). 2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the "Sector/Sector Block Protection and Unprotection" section. 3. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in "Sector/Sector Block Protection and Unprotection". If WP#/ACC = VHH, all sectors will be unprotected. 4. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm. Besides, the WP#/ACC pin must not be left floating or unconnected; otherwise the device may be in inconsistent behavior. ensure data integrity, the Chip Erase command sequence should be reinitiated once the device has returned to reading array data. The system can determine the status of the erase operation by using DQ7, DQ6, or RY/BY#. See "Write Operation Status" for information about these status bits. When the Erase operation is complete, the device returns to reading array data and addresses are no longer latched. Figure 2 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in "AC Characteristics" for parameters. Chip Erase Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Then, two additional unlock write cycles are issued, followed by the chip erase command. The system is not required to provide any controls or timings during these operations. Table 11 shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Chip Erase operation are ignored. Note that a hardware reset during the chip erase operation immediately terminates the operation. In order to Sector Erase Sector erase is a six-bus-cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Then, two additional unlock write cycles This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 10 AC29LV320B/T are issued, followed by the address of the sector to be erased, and the sector erase command. Table 11 shows the address and data requirements for the sector erase command sequence. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 s begins. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 s, otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. A hardware reset during the sector erase operation immediately terminates the operation. In order to ensure data integrity, the Sector Erase command sequence should be reinitiated once the device has returned to reading array data. Figure 2 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the "AC Characteristics" section for parameters, and the Figure 16 for timing diagrams. START Write Erase Command Sequence Data Poll From System No Data = FFh? Yes Erasure Completed Figure 2. Erase Operation Note: See Table 11 for erase command sequence. Page Erase Page erase is a six-bus-cycle operation. The page erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Then, two additional unlock write cycles are issued, followed by the address of the page to be erased, and the page erase command. Table 11 shows the address and data requirements for the page erase command sequence. The system is not required to provide any controls or timings during these operations. separate from the memory array) on DQ7~DQ0. The standard read cycle timings are applied in this mode. The autoselect mode provides manufacturer and device identification, and sector protection verification through identifier codes appearing on outputs DQ7-DQ0. This mode is primarily used for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. Besides, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be set as shown in Table 4. In addition, when verifying sector protection, the sector address must appear properly on the highest order address bits (see Tables 2 and 3). Table 4 shows the remaining address bits that are don't care. After setting all Autoselect Mode When the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 11 AC29LV320B/T necessary bits as required, the programming equipment may then read the corresponding identifier code on DQ7-DQ0. To access the autoselect codes in-system, the host system can also issue the autoselect command via the command register, as shown in Table 11. This method does not require VID. The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 11 shows the address and data requirements. This method is an alternative to that shown in Table 4, which is intended for PROM programmers and requires VID on address pin A9. The autoselect command sequence may be written to an address within a sector that is in the read mode. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times without initiating another command sequence. When device is in word-wide configuration, the read cycles at addresses XX00h, XX03h and XX40h retrieve the manufacturer code, and the read cycle at address XX01h returns the device identification code. When device is in byte-wide configuration, the read cycles at addresses XX00h, XX06h and XX80h retrieve the manufacturer code, and the read cycle at address XX02h returns the device identification code. A read cycle containing a sector address (SA) and the address XX02h in word mode (or XX04h in byte mode) returns 01h if that sector is protected, or 00h if it is unprotected. Refer to Tables 2 and 3 for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data. greater. When in either of these standby modes, the device requires standard access time (tCE) for read access before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in the DC Characteristics table represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes device power consumption. The device enables automatically this mode when addresses are remain stable for tACC + 30ns. The automatic sleep mode is independent of the CE#, WE# and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC5 in the DC Characteristics table represents the automatic sleep mode current specification. Hardware Reset Pin (RESET#) The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, sets all output pins in tri-state, and ignores all read/write commands during the period of RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated after the device is ready to accept another command sequence. This function is to ensure the data integrity. Current is reduced during the period of RESET# pulse. When RESET# is held at VSS 0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS 0.3 V, the standby current will be larger. The RESET# pin may be tied to the system reset circuitry. A system reset would thus reset the device also, enabling the system to read the boot-up firmware from the device. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains at "0" (busy) until the internal reset operation is complete, which requires a time of tREADY. The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (i.e., the RY/BY# pin remains at "1"), the reset operation Standby Mode When the system is not reading from or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state and are independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC 0.3V. Note that this is a more restricted voltage range than VIH. If CE# and RESET# are held at VIH, but not within VCC 0.3V, the device will be in the standby mode, but the standby current will be This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 12 AC29LV320B/T is completed within a time of tREADY. The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# parameters and to Figure 12 for the timing diagram. START Output Disable Mode When the OE# input is at V IH, output from the device is disabled. The output pins are placed in the high impedance state. RESET # = VID (Note 1) Sector/Sector Block Protection and Unprotection Note that the term "sector" applies to both sectors and sector blocks in the following discussion. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Tables 5 and 6). The hardware sector protection can disable both program and erase operations in any sector. The hardware sector unprotection can re-enable both program and erase operations in previously protected sectors. Sector protection/unprotection can be implemented via two methods. The primary method requires VID on the RESET# pin, which can be implemented either in-system or via programming equipment. Figure 4 shows the algorithms and Figure 20 shows the timing diagram. The alternate method mainly for programming equipment requires VID on address pin A9 and OE#. This method is compatible with programmer routines written for earlier 3.0 volt-only Actrans flash devices. The device is shipped with all sectors unprotected. Actrans System Inc. offers the option of programming and protecting sectors at its factory prior to shipping the device. Please contact an Actrans System Inc.'s representative for details. It is possible to determine whether a sector is protected or unprotected. See the Autoselect Mode section for details. Perform Erase or Program Operations RESET # = VIH Temporary Sector Unprotect Completed (Note 2) Figure 3. Temporary Sector Unprotect Operation Notes: 1. All protected sectors are unprotected. (If WP#/ACC = VIL, outermost boot sectors will remain protected). 2. All previously protected sectors are protected once again. unprotected using the method described in "Sector/Sector Block Protection and Unprotection". The two outermost 8 Kbyte boot sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-configured device. If the system asserts VIH on the WP#/ACC pin, the two outermost 8 Kbyte boot sectors of the device reverts to protected or unprotected state that was set previously. That is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in "Sector/Sector Block Protection and Unprotection". Note that the WP#/ACC pin must not be left floating or unconnected to prevent the inconsistent behavior of the device. Write Protect (WP#) The Write Protect function provides a hardware method of protecting certain boot sectors without using VID. This function is one of two provided by the WP#/ACC pin. If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the two "outermost" 8 Kbyte boot sectors regardless of whether those sectors were protected or This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 13 AC29LV320B/T Table 2. AC29LV320T Top Boot Block Sector Address Table Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 Sector Address Sector Size A20-A12 (Kbytes/Kwords) 000000xxx 64/32 000001xxx 64/32 000010xxx 64/32 000011xxx 64/32 000100xxx 64/32 000101xxx 64/32 000110xxx 64/32 000111xxx 64/32 001000xxx 64/32 001001xxx 64/32 001010xxx 64/32 001011xxx 64/32 001100xxx 64/32 001101xxx 64/32 001110xxx 64/32 001111xxx 64/32 010000xxx 64/32 010001xxx 64/32 010010xxx 64/32 010011xxx 64/32 010100xxx 64/32 010101xxx 64/32 010110xxx 64/32 010111xxx 64/32 011000xxx 64/32 011001xxx 64/32 011010xxx 64/32 011011xxx 64/32 011100xxx 64/32 011101xxx 64/32 011110xxx 64/32 011111xxx 64/32 100000xxx 64/32 100001xxx 64/32 100010xxx 64/32 100011xxx 64/32 100100xxx 64/32 100101xxx 64/32 100110xxx 64/32 100111xxx 64/32 101000xxx 64/32 101001xxx 64/32 101010xxx 64/32 101011xxx 64/32 101100xxx 64/32 101101xxx 64/32 (x8) Address Range 000000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh (x16) Address Range 000000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 14 AC29LV320B/T Sector SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 Sector Address Sector Size (x8) A20-A12 (Kbytes/Kwords) Address Range 101110xxx 64/32 2E0000h-2EFFFFh 101111xxx 64/32 2F0000h-2FFFFFh 110000xxx 64/32 300000h-30FFFFh 110001xxx 64/32 310000h-31FFFFh 110010xxx 64/32 320000h-32FFFFh 110011xxx 64/32 330000h-33FFFFh 110100xxx 64/32 340000h-34FFFFh 110101xxx 64/32 350000h-35FFFFh 110110xxx 64/32 360000h-36FFFFh 110111xxx 64/32 370000h-37FFFFh 111000xxx 64/32 380000h-38FFFFh 111001xxx 64/32 390000h-39FFFFh 111010xxx 64/32 3A0000h-3AFFFFh 111011xxx 64/32 3B0000h-3BFFFFh 111100xxx 64/32 3C0000h-3CFFFFh 111101xxx 64/32 3D0000h-3DFFFFh 111110xxx 64/32 3E0000h-3EFFFFh 111111000 8/4 3F0000h-3F1FFFh 111111001 8/4 3F2000h-3F3FFFh 111111010 8/4 3F4000h-3F5FFFh 111111011 8/4 3F6000h-3F7FFFh 111111100 8/4 3F8000h-3F9FFFh 111111101 8/4 3FA0000h-3FBFFFh 111111110 8/4 3FC000h-3FDFFFh 111111111 8/4 3FE000h-3FFFFFh (x16) Address Range 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1F8FFFh 1F9000h-1F9FFFh 1FA000h-1FAFFFh 1FB000h-1FBFFFh 1FC000h-1FCFFFh 1FD000h-1FDFFFh 1FE000h-1FEFFFh 1FF000h-1FFFFFh Note: The address range is A20:A-1 in byte mode (BYTE#=VIL) or A20:A0 in word mode (BYTE#=VIH). This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 15 AC29LV320B/T Table 3. AC29LV320B Bottom Boot Block Sector Addresses Table Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 Sector Address Sector Size A20-A12 (Kbytes/Kwords) 000000000 000000001 000000010 000000011 000000100 000000101 000000110 000000111 000001xxx 000010xxx 000011xxx 000100xxx 000101xxx 000110xxx 000111xxx 001000xxx 001001xxx 001010xxx 001011xxx 001100xxx 001101xxx 001110xxx 001111xxx 010000xxx 010001xxx 010010xxx 010011xxx 010100xxx 010101xxx 010110xxx 010111xxx 011000xxx 011001xxx 011010xxx 011011xxx 011100xxx 011101xxx 011110xxx 011111xxx 100000xxx 100001xxx 100010xxx 100011xxx 100100xxx 100101xxx 100110xxx 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x8) Address Range 000000h-001FFFh 002000h-003FFFh 004000h-005FFFh 006000h-007FFFh 008000h-009FFFh 00A000h-00BFFFh 00C000h-00DFFFh 00E000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh (x16) Address Range 000000h-000FFFh 001000h-001FFFh 002000h-002FFFh 003000h-003FFFh 004000h-004FFFh 005000h-005FFFh 006000h-006FFFh 007000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 16 AC29LV320B/T Sector SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 Sector Address Sector Size A20-A12 (Kbytes/Kwords) 100111xxx 101000xxx 101001xxx 101010xxx 101011xxx 101100xxx 101101xxx 101110xxx 101111xxx 110000xxx 110001xxx 110010xxx 110011xxx 110100xxx 110101xxx 110110xxx 110111xxx 111000xxx 111001xxx 111010xxx 111011xxx 111100xxx 111101xxx 111110xxx 111111xxx 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x8) Address Range 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh (x16) Address Range 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B8000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFFh Note: The address range is A20:A-1 in byte mode (BYTE#=VIL) or A20:A0 in word mode (BYTE#=VIH). Table 4. AC29LV320 Autoseclet Codes (High Voltage Method) A20 A11 to to A9 A12 A10 X X SA X X X VID VID VID A8 to A7 X X X DQ8 to DQ15 A5 to A1 A0 BYTE# BYTE# A2 = VIL = VIH X X X L H L L H L H L H L X 22h X X X X Description CE# OE# WE# A6 L L H L L DQ7 to DQ0 7Fh 7Fh 1Fh 18h (T), 19h (B) 01h (protected) 00h (unprotected) Manufacturer ID: ACTRANS Device ID: AC29LV320 Sector Protection Verification L L L L L L H H H Legend: T = Top Boot Block, B = Bottom Boot Block, L = Logic Low = VIL, H = Logic High = V IH, SA = Sector Address, X = Don't care. This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 17 AC29LV320B/T Table 5. Top Boot Sector/Sector Block Addresses for Protection/Unprotection Sector SA0-SA3 SA4-SA7 SA8-SA11 SA12-SA15 SA16-SA19 SA20-SA23 SA24-SA27 SA28-SA31 SA32-SA35 SA36-SA39 SA40-SA43 SA44-SA47 SA48-SA51 SA52-SA55 SA56-SA59 SA60-SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 A20-A12 000000XXX 000001XXX 000010XXX 000011XXX 0001XXXXX 0010XXXXX 0011XXXXX 0100XXXXX 0101XXXXX 0110XXXXX 0111XXXXX 1000XXXXX 1001XXXXX 1010XXXXX 1011XXXXX 1100XXXXX 1101XXXXX 1110XXXXX 111100XXX 111101XXX 111110XXX 111111000 111111001 111111010 111111011 111111100 111111101 111111110 111111111 Sector/Sector Block Size 256 (4 x 64) Kbytes 256 (4 x 64) Kbytes 256 (4 x 64) Kbytes 256 (4 x 64) Kbytes 256 (4 x 64) Kbytes 256 (4 x 64) Kbytes 256 (4 x 64) Kbytes 256 (4 x 64) Kbytes 256 (4 x 64) Kbytes 256 (4 x 64) Kbytes 256 (4 x 64) Kbytes 256 (4 x 64) Kbytes 256 (4 x 64) Kbytes 256 (4 x 64) Kbytes 256 (4 x 64) Kbytes 192 (3 x 64) Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 18 AC29LV320B/T Table 6 Bottom Boot Sector/Sector Block Addresses for Protection/Unprotection Sector SA70-SA67 SA66-SA63 SA62-SA59 SA58-SA55 SA54-SA51 SA50-SA47 SA46-SA43 SA42-SA39 SA38-SA35 SA34-SA31 SA30-SA27 SA26-SA23 SA22-SA19 SA18-SA15 SA14-SA11 SA10-SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 A20-A12 111111XXX 111110XXX 111101XXX 111100XXX 1110XXXXX 1101XXXXX 1100XXXXX 1011XXXXX 1010XXXXX 1001XXXXX 1000XXXXX 0111XXXXX 0110XXXXX 0101XXXXX 0100XXXXX 0011XXXXX 0010XXXXX 0001XXXXX 000011XXX 000010XXX 000001XXX 000000111 000000110 000000101 000000100 000000011 000000010 000000001 000000000 Sector/Sector Block Size 256 (4 x 64) Kbytes 256 (4 x 64) Kbytes 256 (4 x 64) Kbytes 256 (4 x 64) Kbytes 256 (4 x 64) Kbytes 256 (4 x 64) Kbytes 256 (4 x 64) Kbytes 256 (4 x 64) Kbytes 256 (4 x 64) Kbytes 256 (4 x 64) Kbytes 256 (4 x 64) Kbytes 256 (4 x 64) Kbytes 256 (4 x 64) Kbytes 256 (4 x 64) Kbytes 256 (4 x 64) Kbytes 192 (3 x 64) Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 19 AC29LV320B/T Temporary Sector Unprotect This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID (11.5V~12.5V). During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 3 shows the algorithm, and Figure 19 shows the timing diagrams of this feature. power-up. Write Operation Status The device provides several bits to determine the status of a program or erase operation: DQ6, DQ7, and RY/BY#. Table 12 and the following subsections describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether a Program or Erase operation is in progress or has been completed. Hardware Data Protection The command sequence with the requirement of unlock cycles for programming or erasure provides data protection against inadvertent writes (refer to Table 11 for command definitions). In addition, the following hardware data protection features can prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC powerup and power-down transitions, or from system noise. Data# Polling (DQ7) The Data# Polling bit, DQ7, indicates whether a Program or Erase operation is in progress or completed. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command sequence. During the Program operation, the device output on DQ7 is complement to the datum programmed to DQ7. When the Program operation is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1s, then the device returns to reading array data. During the Erase operation, Data# Polling produces a "0" on DQ7. When the Erase operation is complete, Data# Polling produces a "1" on DQ7. This is analogous to the complement/true datum output described for the Program operation: the erase function changes all the bits in a sector to "1"; prior to this, the device outputs the "complement", or "0". The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 s, then the device returns to reading array data. If not all selected sectors are protected, the Erase operation erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. This feature protects data during VCC power-up and power-down. When VCC becomes greater than VLKO, the system must provide the proper signals to the control pins to prevent unintentional writes. Noise/Glitch Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Write Inhibit Mode Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH, or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE#=CE#=VIL and OE#=VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 20 AC29LV320B/T START START PLSCNT=1 RESET#=V ID W AIT 1us P ro tect all secto rs: The indicated portion of the sector protect algorithm m ust be perform ed for all unprotected sectors prior to issuing the first sector unprotect addressl PLSCNT=1 RESET#=V ID W AIT 1us Tem porary Sector Unprotect Mode No First W rite Cycle=60h? Yes Set up sector address Sector Protect: W rite 60h to sector address with A6=0, A1=1, A0=0 W ait 150 us Verify Sector Project: W rite 40h to sector address with A6=0, A1=1, A0=0 Read from sector address with A6=0, A1=1, A0=0 First W rite Cycle=60h? Yes No All sectors protected? Yes Set up first sector address Sector Unprotect: W rite 60h to sector address with A6=1, A1=1, A0=0 W ait 15 m s Verify Sector Unprotect: W rite 40h to sector address with A6=1, A1=1, A0=0 No Tem porary Sector Unprotect Mode Reset PLSCNT=1 Increm ent PLSCNT Increm ent PLSCNT PLSCNT = 25? No Data=01h? Read from sector address with A6=1, A1=1, A0=0 Set up next sector address Yes Protect another sector No Rem ove V ID from RESET# W rite reset com m and Device Failed Yes PLSCNT =1000? No Data=00h? Device failed Yes Last sector verified? Yes No S ector Protect Algorithm Sector Protect com plete S ector U nprotect Algorithm Rem ove V ID from RESET# W rite reset com m and Sector Unprotect com plete Figure 4. In-S ystem S ector P rotect /U nprotect Algorithm This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 21 AC29LV320B/T START Read DQ7-DQ0 Addr = VA an open-drain output, several RY/BY# pins can be tied together in parallel and connect to VCC with a pull-up resistor. If the output is low (Busy), the device is actively erasing or programming. If the output is high (Ready), the device is ready to read array data, or is in the standby mode. Toggle Bit (DQ6) No DQ7 = Data? Yes PASS Figure 5. Data# Polling Algorithm Notes: VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. Just prior to the completion of a Program or Erase operation, DQ7 may change asynchronously with DQ0-DQ6 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Thus, depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ0-DQ6 may be still invalid. The valid data on DQ0-DQ7 will appear on successive read cycles. Table 12 shows the outputs for Data# Polling on DQ7. Figure 5 shows the Data# Polling algorithm. Figure 17 in the AC Characteristics section shows the Data# Polling timing diagram. The "Toggle Bit" on DQ6 indicates whether a Program or Erase operation is complete or in progress. Toggle Bit may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During a Program or Erase operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 s, then returns to reading array data. If not all selected sectors are protected, the Erase operation erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 to determine whether a sector is actively erasing. When the device is actively erasing (i.e., the Erase operation is in progress), DQ6 toggles. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. Table 12 shows the outputs for Toggle Bit on DQ6. Figure 6 shows the toggle bit algorithm. Figure 18 in the "AC Characteristics" section shows the toggle bit timing diagrams. COMMON FLASH MEMORY INTERFACE (CFI) The Common Flash Interface (CFI) specification outlines the device and the host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for the entire families of the devices. Software support can then be device-independent, Ready/Busy# (RY/BY#) The RY/BY# is a dedicated, open-drain output pin that indicates whether a Program or Erase operation is complete or in progress. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 22 AC29LV320B/T START Read DQ7-DQ0 Note Read DQ7-DQ0 Yes Toggle Bit (DQ6) = Toggle? No Program/Erase Operation Complete JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 7-10. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 7-9. The system must write the reset command to return the device to the autoselect mode. Figure 6. Toggle Bit Algorithm Notes: Read toggle bit twice to determine whether or not it is toggling (see text). This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 23 AC29LV320B/T Table 7 CFI Query Identification String Addresses (Word Mode) 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Addresses (Byte Mode) 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h Description Query Unique ASCII string "QRY" Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) Table 8. System Interface String Addresses (Word Mode) 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Addresses (Byte Mode) 36h 38h 3Ah 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch Data 0027h 0036h 0000h 0000h 0004h 0000h 0004h 0008h 0001h 0000h 0002h 0002h Description VCC Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VCC Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VPP Min. Voltage (00h=no VPP pin present) VPP Max. Voltage (00h=no VPP pin present) N Typical timeout per single byte/word write 2 s N Typical timeout for Min size buffer write 2 s (00h = not supported) N Typical timeout per individual block erase 2 ms N Typical timeout for full chip erase 2 ms (00h = not supported) N Max. timeout for byte/word write 2 times typical N Max. timeout for buffer write 2 times typical N Max. timeout per individual block erase 2 times typical N Max. timeout for full chip erase 2 times typical (00h = not supported) This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 24 AC29LV320B/T Table 9 Device Geometry Definitions Addresses (Word Mode) 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Addresses (Byte Mode) 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 78h Data 0016h 0002h 0000h 0000h 0000h 0002h 0007h 0000h 0020h 0000h 003Eh 0000h 0000h 0001h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h N Description Device Size = 2 byte Flash Device Interface description Max. number of byte in multi-byte write = 2 (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information N Erase Block Region 2 Information Erase Block Region 3 Information Erase Block Region 4 Information This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 25 AC29LV320B/T Table 10. Primary Vendor-Specific Extended Query Addresses (Word Mode) 40h 41h 42h 43h 44h 45h Addresses (Byte Mode) 80h 82h 84h 86h 88h 8Ah Data 0050h 0052h 0049h 0031h 0031h 0000h Description Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock (Bits 1-0) 0=Required, 1 = Not required Silicon Revision Number (Bits 7-2) Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write) Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 04 = 29LV800 mode Simultaneous Operation 00 = Not Supported, Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page 02 = 8 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 02h= Bottom Boot Device, 03h= Top Boot Device 46h 8Ch 0000h 47h 48h 49h 4Ah 4Bh 4Ch 8Eh 90h 92h 94h 96h 98h 0004h 0001h 0004 0000h 0000h 0000h 4Dh 9Ah 0000h 4Eh 4Fh 9Ch 9Eh 0000h 000Xh This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 26 AC29LV320B/T Table 11. AC29LV320 Command Definitions Command Sequence (Note 1) Read (Note 6) Reset (Note 7) Word Byte Word Manufacturer ID Byte Word Byte Device ID, Top Boot Word Block Byte Device ID, Bottom Word Boot Block Byte Sector/Sector Block Protect Verify (Note 9) Program Word 4 Byte Bus Cycles (Notes 2-5) First Second Third Fourth Fifth Sixth Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data RA RD XXX F0 555 2AA 555 X00 AA 55 90 7F AAA 555 AAA X00 555 2AA 555 X03 AA 55 90 7F AAA 555 AAA X06 555 2AA 555 X40 AA 55 90 1F AAA 555 AAA X80 555 2AA 555 X01 2218 AA 55 90 AAA 555 AAA X02 18 555 2AA 555 X01 2219 AA 55 90 AAA 555 AAA X02 19 (SA) 555 2AA 555 X02 00/ AA 55 90 01 (SA) AAA 555 AAA X04 555 2AA 555 AA 55 A0 PA PD AAA 555 AAA 555 2AA 555 AA 55 20 AAA 555 AAA XXX PA 555 AAA 555 AAA 555 AAA 55 AA A0 90 AA AA AA 98 PA XXX 2AA 555 2AA 555 2AA 555 PD 00 55 55 55 555 AAA 555 AAA 555 AAA 80 80 80 555 AAA 555 AAA 555 AAA AA AA AA 2AA 555 2AA 555 2AA 555 55 55 55 555 AAA SA PEA 10 30 20 Cycle 1 1 4 4 4 4 4 Word 4 Byte Word Unlock Bypass 3 Byte Unlock Bypass Program (Note 2 10) Unlock Bypass Reset 2 (Note 11) Word Chip Erase 6 Byte Word Sector Erase 6 Byte Word Page Erase 6 Byte CFI Query Word 1 (Note 12) Byte Legend: X = Don't care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A20-A12 uniquely select any sector. PEA = Address of the page to be erased. Address bits A20-A8 uniquely select any page. Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. Autoselect (Note 8) This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 27 AC29LV320B/T 3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. Data bits DQ15-DQ8 are don't care in command sequences, except for RD and PD. 5. Unless otherwise noted, address bits A20-A11 are don't cares. 6. No unlock or command cycles required when device is reading array data. 7. The Reset command is required to return to the read mode when a device is in the autoselect mode. 8. The fourth cycle of the autoselect command sequence is a read cycle. Data bits DQ15-DQ8 are don't care. See the Autoselect Command Sequence section for more information. 9. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. 10. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 11. The Unlock Bypass Reset command is required to return to the read mode when the device is in the unlock bypass mode. 12. Command is valid when device is ready to read array data or when device is in autoselect mode. Table 12. Write Operation Status Status Program Erase DQ7 (Note) DQ7# 0 DQ6 Toggle Toggle RY/BY# 0 0 Note: DQ7 requires a valid address when reading status information. Refer to the appropriate subsection for further details. This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 28 AC29LV320B/T ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages .................................................................. -65C to 150C Ambient Temperature with Power Applied. ................................................................ -65C to 125C Voltage with Respect to Ground VCC (Note 1).......................................................... -0.5 V to +4.0 V A9, OE#, and RESET# (Note 2).......................................................................... -0.5 V to +12.5 V All Other Pins (Note 1)................................................................................... -0.5 V to VCC +0.5 V Output Short Circuit Current (Note 3)................................................................................. 200 mA Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 8. Minimum DC input voltage on pins A9, OE#, WP#/ACC and RESET# is -0.5 V. During voltage transitions, A9, OE#, WP#/ACC and RESET# may overshoot V SS to -2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC input voltage on pin A9 is +12.5 V, which may overshoot to 14.0 V for periods up to 20 ns. Maximum DC input voltage on WP#/ACC is 9.5V which may overshoot to +12.0V for periods up to 20ns. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 2. 3. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 20 ns +0.8 V - 0.5 V 20 ns 20 ns VCC + 2.0 V VCC + 0.5 V 2.0 V - 2.0 V 20 ns 20 ns 20 ns Figure 7. Maximum Negative Overshoot Waveform Figure 8. Maximum Positive Overshoot Waveform OPERATING RANGES Commercial (C) Devices Ambient Temperature (TA)...............0C to 70C Industrial (I) Devices Ambient Temperature (TA)...........-40C to 85C Extended (E) Devices Ambient Temperature (TA).........-55C to 125C VCC Supply Voltages VCC for full voltage range.............. 2.7 V to 3.6 V Operating ranges define those limits between which the functionality of the device is guaranteed. This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 29 AC29LV320B/T DC CHARACTERISTICS CMOS Compatible Parameter ILI ILIT ILO Description Input Load Current A9 Input Load Current Output Leakage Current Test Conditions VIN=VSS to VCC, VCC=VCC max VCC=VCC max; A9=12.5V VOUT=VSS to VCC, VCC=VCC max CE#=VIL, 5 MHz OE#=VIH, 1 MHz Byte Mode CE# =VIL, 5 MHz OE# =VIH, 1 MHz Word Mode CE#=VIL, OE#=VIH WE#=VIL CE#, Reset#=VCC0.3V Reset#=VSS0.3V VIH=VCC0.3V; VIL=VSS0.3V CE#=VIL, OE#=VIH ACC pin VCC pin -0.5 0.7 x VCC 9 9 Min Typ Max 3.0 35 1.0 10 2 10 2 15 0.2 0.2 0.2 5 15 16 4 16 4 30 5 5 5 10 30 0.8 VCC +0.3 12.5 12.5 0.45 0.85 VCC VCC-0.4 2.3 2.5 mA A A A mA mA V V V V V V V V mA Unit A A A ICC1 VCC Active Read Current (Note 1,2) ICC2 ICC3 ICC4 ICC5 IACC VIL VIH VHH VID VOL VOH1 VOH2 VLKO VCC Active Write Current (Note 2, 3) VCC Standby Current (Note 2) VCC Reset Current (Note 2) Automatic Sleep Mode (Notes 2, 4) ACC Accelerated Program Current, Word or Byte Input Low Voltage Input High Voltage Voltage for WP#/ACC Sector Protect /Unprotect and VCC=3.0 V 10% Program Acceleration Voltage for Autoselect and VCC=3.0 V 10% Temporary Sector Unprotect Output Low Voltage Output High Voltage Low VCC Lock-Out Voltage (Note 5) IOL=4.0mA, VCC=VCC min IOH=-2.0mA, VCC=VCC min IOH=-100A, VCC=VCC min Notes: 1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. Maximum ICC specifications are tested with VCC = VCC max. 3. ICC active while Erase or Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 5. Not 100% tested. This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 30 AC29LV320B/T TEST CONDITIONS 3.3V Table 13. Test Specifications Test Conditions Output Load Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels 90 30 120 Unit 1 TTL gate 100 pF ns V V V 2.7K Device Under Test CL 6.2K 5 0.0-3.0 1.5 1.5 Note: Diodes are IN3064 or equivalent Figure 9. Test Setup KEY TO SWITCHING WAVEFORMS Waveform Inputs Steady Outputs Changing from H to L Changing from L to H Don't care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is high Impedance State (High Z) 3.0V Input 1.5V 0.0V Measurement Level 1.5V Output Figure 10. Input Waveforms and Measurement Levels This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 31 AC29LV320B/T AC CHARACTERISTICS Read Operations Parameter JEDEC Std Description Read Cycle Time (Note 1) Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High Z (Note 1) Output Enable to Output High Z (Note 1) Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 1) Read Output Enable Toggle and Hold Time (Note 1) Data# Polling Test Setup CE#=VIL, OE#=VIL OE#=VIL Min Max Max Max Max Max Min Min Min Speed Options 90 120 90 120 90 120 90 120 40 50 30 30 30 30 0 0 10 Unit ns ns ns ns ns ns ns ns ns tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX tRC tACC tCE tOE tDF tDF tOH tOEH Notes: 1. Not 100% tested. 2. See Figure 9 and Table 13 for test specifications. tR C Addresses Addresses Stable t A CC CE# tO E t RH t OE H W E# HIGH Z tC E Output Valid t OH HIG H Z t DF OE# tR H Outputs RESET# AC Characteristics R Y / B YV 0# Figure 11. Read Operation Timings This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 32 AC29LV320B/T AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std Description RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) RESET# Pin Low (Not During Embedded Algorithms) to Read Mode (See Note) RESET# Pulse Width Reset High Time Before Read (See Note) RESET# Low to Standby Mode RY/BY# Recovery Time Max Max Min Min Min Min All Speed Unit Options 20 500 500 50 20 0 s ns ns ns s ns tREADY tREADY tRP tRH tRPD tRB Note: Not 100% tested. RY/BY# CE#,OE# t RH RESET# Reset Timings NOT during Embedded Algorithms t RP t READY Reset Timings NOT during Program or Erase operations Reset Timings during Program or Erase RY/BY# tREADY tRB CE#,OE# RESET# tRP Figure 12. Reset# Timings This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 33 AC29LV320B/T AC CHARACTERISTICS Word/Byte Configurations (Byte#) Parameter JEDEC Std tELFL/tELFH Description CE# to Byte# Switching Low or High BYTE# Switching Low to Output HIGH Z BYTE# Switching High to Output Active Max Max Min Speed Options Unit 90 120 5 ns 30 30 ns 90 120 ns tFLQZ tFHQV C E# O E# BYT E# D Q 0-D Q 14 BYT E# Switching from word to byte mode t ELFL D Q 15/A-1 Data Output (D Q 0-D Q 14) Data Output (D Q 0-D Q 7) D Q 15 O utput t FLQ Z t ELFH Address Input BYT E# BYT E# Switching from byte to word mode D Q 0-D Q 14 Data Output (D Q 0-D Q 7) Data Output (D Q 0-D Q 14) D Q 15/A-1 Address Input t FH Q V D Q 15 O utput Figure 13. BYTE# Timings for Read Operations CE# The falling edge of the last W E# signal OE# BYTE# t S ET (t AS ) t HO LD (tAH ) N o te: Refer to the Erase/Program Operations table for t AS and t AH specifications Figure 14. BYTE# Timings for Write Operations This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 34 AC29LV320B/T AC CHARACTERISTICS Erase/Program Operations Parameter JEDEC Std Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Read Recovery Time Before Write (OE# High to WE# Low) CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Programming Operation Byte (Note 2) Word Sector Erase Operation (Note 2) VCC Setup Time (Note 1) Write Recovery Time from RY/BY# Program/Erase Valid to RY/BY# Delay Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Min Min Min Speed Options 90 120 90 120 0 45 50 45 50 0 0 0 0 0 35 30 9 11 20 50 0 90 50 Unit ns ns ns ns ns ns ns ns ns ns ns s ms s ns ns tAVAV tAVWL tWLAX tDVWH tWHDX tGHWL tELWL tWHEH tWLWH tWHDL tWHWH1 tWHWH2 tWC tAS tAH tDS tDH tOES tGHWL tCS tCH tWP tWPH tWHWH1 tWHWH2 tVCS tRB tBUSY Notes: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information. This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 35 AC29LV320B/T AC CHARACTERISTICS tW C Addresses 555h tAS PA t AH PA PA CE# t CH OE# tGHWL tW P W E# t CS t W HW H1 t W PH t DS Data A0h t DH PD Status D OUT tBUSY t RB RY/BY# V CC t VCS Notes: 1. PA= program address, PD=program data, DOUT is the true data at the program address. 2. Illustration shows device in word mode. Figure 15. Program Operation Timings This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 36 AC29LV320B/T AC CHARACTERISTICS Erase Com m and Sequence (last two cycles) tW C Addresses 2AAh t AS SA 555h for chip erase Read Status Data VA t AH VA CE# OE# t CH t CS tW P t W PH t DS t DH 30h 10 for chip Erase W E# t W HW H2 In Progress Com plete Data 55h t BUSY t RB RY/BY# t V CS V CC Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operation Status") 2. Illustration shows device in word mode. Figure 16. Chip/Sector Erase Timings This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 37 AC29LV320B/T AC CHARACTERISTICS tRC Addresses VA tACC tCE CE# tCH OE# tOEH W E# tOH DQ7 Complement Complement True Valid Data High Z tDF tOE VA VA DQ0-DQ6 tBUSY RY/BY# Status Data Status Data True Valid Data High Z Note: VA=Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. Figure 17. Data# Polling Timings tAHT Addresses tASO CE# WE# OE# tDH DQ6/DQ2 RY/BY# Valid Data Valid Status (first read) tOE Valid Status Valid Status (stops toggling) tOEH tOEPH tAHT tCEPH tAS Valid Data (second read) Note: VA=Valid address; not required for DQ6. Illustration shows first two status cycles after command sequences, last status read cycle, and array data read cycle. Figure 18. Toggle Bit Timings This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 38 AC29LV320B/T AC CHARACTERISTICS Temporary Sector Unprotect Parameter JEDEC Std Description Min Min Min Min All Speed Options 500 250 4 4 Unit ns ns s s VID Rise and Fall Time (See Note) VHH Rise and Fall Time (See Note) RESET# Setup Time for Temporary Sector tRSP Unprotect RESET# Hold Time from RY/BY# High for tRRB Temporary Sector Unprotect Note: Not 100% tested. tVIDR tVHH V ID RESET# V SS , V IL or V IH V ID t VIDR V S S , V IL or V IH Program or Erase Com m and Sequence t VIDR CE# t RSP W E# t RRB RY/BY# Figure 19. Temporary Sector Unprotect Timing Diagram This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 39 AC29LV320B/T AC CHARACTERISTICS V ID RESET# V IH SA, A6, A1, A0 Valid* Sector Protect/Unprotect Valid* Verify 40h Valid* Data 60h 1s 60h Status Sector/Sector Block Protect: 150 s Sector/Sector Block Unprotect: 15m s CE# W E# OE# *For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0 Figure 20. Sector/Sector Block Protect and Unprotect Timing Diagram This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 40 AC29LV320B/T AC CHARACTERISTICS Alternate CE# Controlled Erase/Program Operations Parameter JEDEC Std Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time CE# Pulse Width CE# Pulse Width High Programming Operation Byte (Note 2) Word Sector Erase Operation (Note 2) Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Speed Options 90 120 90 120 0 45 50 45 50 0 0 0 0 0 45 30 9 11 20 50 Unit ns ns ns ns ns ns ns ns ns ns ns s ms tAVAV tAVWL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH2 tWC tAS tAH tDS tDH tOES tGHEL tWS tWH tCP tCPH tWHWH1 tWHWH2 Notes: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information. This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 41 AC29LV320B/T AC CHARACTERISTICS tRC 555 for Program 2AA for erase CE# Address Stable PA for Program SA for sector erase 555 for chip erase t ACC Data# Polling tRH Addresses OE# tW C tW H W E# WE# tRH t AS tDF PA tOE t AH tOEH tCE tOH Output Valid HIGH Z Outputs OE# HIGH Z t GHEL RESET# CE# t CP t W HW H1 or 2 t CPH RY/BY# 0V tW S t DS t BUSY t DH DQ7# D OUT Data t RH RESET# A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase RY/BY# Notes: 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA=program address, SA=sector address, PD=program data. 3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device. 4. Waveforms are for the word mode. Figure 21. Alternate CE# Controlled Write (Erase/Program) This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 42 AC29LV320B/T Erase and Programming Performance Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 20 ms Chip Erase Time 500 ms Byte Program Time 9 20 s Accelerated Byte/Word Program s 7 18 Time Excludes system level Word Program Time 11 22 s overhead (Note 3) Byte Mode 30 Chip Program Time sec Word Mode 24 Notes: 1. Typical program and erase times assume the following conditions: 25C, 3.0 V VCC, 100,000 cycles. Additionally, programming typical assume checkerboard pattern. 2. Under worst-case conditions of 90C, VCC = 2.7 V, 100,000 cycles. 3. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 11 for further information on command definitions. 4. The device has a typical erase and program cycle endurance of 100,000 cycles. LATCHUP CHARACTERISTICS Description Min Max Input voltage with respect to VSS on all pins expect I/O -1.0V 12.5V pins (including A9, OE#, and RESET#) Input voltage with respect to VSS on all I/O pins -1.0V VCC + 1.0V VCC Current -100mA +100mA Notes: Includes all pins except VCC. Test conditions: VCC =3.0V, one pin at a time. TSOP AND SO PIN CAPACITANCE Parameter Symbol Parameter Description CIN Input Capacitance COUT Output Capacitance CIN2 Control Pin Capacitance Notes: 1. Samples, not 100% tested. 2. Test conditions TA=25C, f=1.0MHz. Test Setup VIN=0 VOUT=0 VIN=0 Typ Max Unit 6 7.5 pF 8.5 12 pF 7.5 9 pF DATA RETENTION Parameter Minimum Pattern Data Retention Time Test Conditions 150C 125C Min 10 20 Unit Years Years This preliminary data sheet contains product specifications which are subject to change without notice. AC29LV320B/T Page 43 |
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